In a television broadcast, a television multicharacter broadcast has been considered in which various informations such as news, weather forecast, announcement and so on are broadcast by utilizing the vertical blanking period of the television broadcast. As an example thereof, there is proposed a format shown in FIGS. 1 to 3.
The format shown in the figures is a format used by NHK(Nippon Hoso Kyokai), the Japanese broadcast association. As shown in FIG. 1, picture elements of 248 dots form one horizontal line, 204 lines thereof constitute one page and one page forms one picture screen. However, one picture element takes a binary digit of "1" or "0". Further, picture elements of 8 dots.times.12 dots (lines) are called as one sub-block so that one page includes 31.times.17 sub-blocks. And, color is appointed at the unit of one sub-block. Further, the number of pages is selected, for example, about several tens and the data of several ten pages are delivered repeatedly.
The data signal thereof is delivered as a serial digital signal as shown in FIG. 2A during the 20th horizontal period (in case of an odd field period) and the 283rd horizontal period (in case of an even field period) in the vertical blanking period. The data signal of a desired page is delivered at every one page in the following manner.
That is, as shown in FIG. 3A, during the first field period a page control packet PCP is delivered. As shown in FIG. 2B, this packet PCP includes in its header portion of 48 bits a clock run-in CR, a framing code FC and other control signals and in its data portion of 248 bits a page control signal representing to which page this data signal belongs and so on.
During the second field period, delivered is a color code packet CCP. As shown in FIG. 2C, this packet CCP includes in its data portion a row code representing to which sub-blocks of row orders the following 12 packets belong and a color code appointing the color of each sub-block at the unit of one sub-block. In this case, the color code consists of 4 bits per one sub-block and appoints the color of the sub-block.
Further, during the third to 14th field periods, 12 pattern data packets PDP are sequentially delivered. As shown in FIG. 2D, the packets PDP comprise in the data portion thereof picture elements of 1st to 12th lines in 31 sub-blocks of 1 line. For example, the first pattern data packet PDP, which is delivered during the third field period, sequentially includes in its data portion the picture elements in the first lines of the respective sub-blocks of the first line.
Accordingly, by the packets delivered during the second to 14th field periods, all the picture elements of the sub-blocks on the first line of one page and their colors are completed.
Similarly, the sub-blocks of one line are delivered by one color code packet CCP and 12 pattern data packets PDP following thereto.
By this manner, when during the 222nd field period the picture elements on the 12th line of the 17th sub-block are delivered by the packet PDP, the data of one page are thereby delivered.
Accordingly, the data of one page are delivered by one page control packet PCP, 17 color code packets CCP and 204 (=12.times.17) pattern data packets PDP, in which 204 pattern data packets PDP correspond to the picture elements of FIG. 1.
As set forth above, during 222 field periods 222 packets are delivered and hence the data of one page are delivered. When such the operation will be repeated for each of pages as shown in FIG. 3B as well as the data of all the pages will be delivered, the data will be delivered again from the first page.
As described above, the character broadcast signal of the F-mode is delivered. The packet construction of other S-, V- and H-modes is substantially same as that of the above.
The television receiver for receiving the character broadcast with the afore-mentioned format is constructed, for example, as shown in FIG. 4.
That is, in FIG. 4, 10 generally designates a video signal system, 11 a tuner, 12 a video intermediate frequency amplifier, and 13 a video detecting circuit. Upon receiving a usual television broadcast, the color video signal from the detecting circuit 13 is fed to a video circuit 14 which then produces three primary color signals which are supplied through a switch circuit 15, which will be described later, to a color cathode ray tube 16 on which a color image is reproduced.
In FIG. 4, 20 generally designates a micro-computer which controls the reproduction of the character broadcast. That is, 21 denotes a CPU of, for example, 8-bit parallel processing type, 22 a ROM on which written is a program for receiving the character broadcast, and 23 a RAM for a work area, which are connected through a data bus 24 and an address bus 25.
30 generally designates a reproducing circuit for the character broadcast. 33 designates a buffer memory having the capacity of one packet, 34 and 35 display memories each having the capacity of one page. The memory 34 is used to memorize the pattern data, while the memory 35 is used to memorize the color code. Further, 41 shows a key board. This key board 41 comprises a key (switch) for switching a mode for receiving the usual television broadcast and a mode for receiving the character broadcast, a key for selecting a page and so on. The output from the key board is delivered through an interface 38 to the data bus 24 and also to a timing signal generating circuit 42. This generating circuit 42 is formed of a PLL, a counter, a logic circuit and so on, is supplied with the video signal from the detecting circuit 13 as well as vertical and horizontal synchronizing pulses Pv and Ph from a synchronous separating circuit 43 and then generates various signals such as an address signal upon the writing of the memory 33, an address signal upon reading the memories 34 and 35 and so on in synchronism with the above synchronizing pulses and the clock run-in CR. A flag showing the vertical scanning period and vertical fly-back period is fed from the generating circuit 42 to the CPU 21 which in turn supplies a flag representing the ends of various processes and a system control signal to the generating circuit 42.
The video signal from the detecting circuit 13 is supplied to a serial-in/parallel-out shift register 31 of 8 bits in which the packet is converted from a serial signal to a parallel signal at every 8 bits. The parallel signal therefrom is fed to a gate circuit (3-state buffer) 32 which is also supplied with a pulses P42 as the control signal which is provided by the generating circuit 42 and becomes "1" during the horizontal periods (20th and 283rd horizontal periods) from which the signal of the packet is delivered to the data bus 24 in parallel 8 bits by 8 bits.
Also, at this time, the pulse P42 is supplied to the CPU 21 as the holding signal so that the CPU 21 is made in the holding state during the horizontal period of the packet, and this pulse P42 is fed to a change-over gate 46 as the control signal so that the address signal from the generating circuit 42 is applied to the memory 33 through the gate 46.
Accordingly, the signal of the packet is transferred 8 bits by 8 bits and in parallel from the register 31 through the gate circuit 32 and the data bus 24 to the memory 33 by the manner of DMA and then written in the memory 33 sequentially.
When the horizontal period of the packet is terminated, P42="0" is established and the register 31 is disconnected from the data bus 24 by the gate 32. At this time, the CPU 21 is released from the holding state thereof and the address bus 25 is connected to the memory 33 through the change-over gate 46.
Then, the data from the memory 33 is processed by the CPU 21 in accordance with the program of the ROM 22 and it is judged whether or not the data are those of a desired page inputted from the key board 41 by the page control signal. If the data are not the data of the desired page, the data are neglected.
The above operation will be repeated at every field until the packet of the desired page is delivered.
When the data from the memory 33 is that of the packet of the desired page, the following operation is carried out. That is, when the packet CCP is delivered, this packet is written in the memory 33 by the DMA similar to the above. Then, when the writing of the packet CCP is finished and the CPU 21 is released from the holding state, the data of the memory 33 is processed by the CPU 21, the color code is read out from the memory 33 and then written in the memory 35 through the data bus 24. This write-in is carried out by such a manner that during the same vertical fly-back period, the address bus 25 is connected through a change-over gate 47 to the memory 35, and the address of the memory 35 is appointed by the CPU 21.
Further, when the packet PDP is transmitted, this packet is written in the memory 33 by the DMA and then only the pattern data are transferred from the memory 33 to the memory 34 during the vertical fly-back period by the processing of the CPU 21. The address appointment of the memory 34 is carried out by the CPU 21, too.
As set forth above, when packets CCP and PDP of the desired page are delivered, these packets are once stored in the memory 33 by the DMA and then only the necessary data are transferred to the memories 34 and 35 by the CPU 21 and then written therein.
When the data of the last packet of the desired page are transferred to the memory 34, the CPU 21 is again made in a standby state for a desired page.
While, during the vertical scanning period, the control signal is supplied from the generating circuit 42 to the change-over gate 47, the address signal from the generating circuit 42 is supplied to the memories 34 and 35 through the change-over gate 47 and the color code and pattern data of the memories 35 and 34, respectively are read out simultaneously.
The pattern data read out from the memory 34 are fed to a parallel-in/serial-out shift register 36 of 8 bits and then converted thereby from the parallel signal to the serial signal which is then fed to a color generator 37 to which the color code read out from the memory 35 is applied. Thus, the data signal is made as three primary color signals thereby and then supplied to the switch circuit 15. At this time, the control signal is applied from the generating circuit 42 to the switch circuit 15 so that the switch circuit 15 is switched to the side of the generator 37.
Accordingly, the desired page of the character broadcast is displayed on the color cathode ray tube 16.
As explained above, the television receiver shown in FIG. 4 receives the character broadcast.
By the way, since the above character broadcast requires 222 field periods i.e. 3.7 seconds for transmitting the image of one page, the waiting time from the input of the number of a desired page to the display thereof becomes long sometimes and longer than 30 seconds at the worst.
Therefore, such a method has been considered that the capacities of the memories 34 and 35 are each made as, for example, largeness of 4 page amounts of areas #0, #1, #2 and #3 as shown in FIG. 5 and pages which are required frequently are always received and respectively written in the areas #0 to #3. That is, according to this method, if the area of those #0 to #3 in which a necessary page is already written is selectively read out, the necessary page can be immediately displayed.
Accordingly, according to this method, if a page which is required frequently, for example, program guide, announcement and so on of the character broadcast is desired to be displayed, such page can be seen at once, which is very convenient.
However, if such method is employed, very high speed memories are required to be used for the pattern data memory 34 and color code memory 35.
Additionally, the page control packet PCP sometimes contains an "erasing code" which functions as a control code. Thus, when a certain page is appointed, if the page control packet PCP of this page contains the erasing code, it is necessary that within one field period, during which the next packet is delivered, the data of all "0" are set on the pattern memory 34 as the erasing data and the color data of all "white" are set on the color memory 35.
When the capacity of the memories 34 and 35 is one page amount, the capacity of the memory 34 is
248.times.204=50592 bits PA1 31.times.17.times.4=2108 bits
and that of the memory 35 is
If the capacities are set as above, within one field period before the next packet is transmitted, erasing data can be set.
However, in the case that the memories 34 and 35 have the capacity for 4 page amounts of areas #0 to #3 as shown in FIG. 5, if while the data of the area #0 are displayed, the erasing code for the area #1 is transmitted, it is necessary that while the data read-out for the area #0 is carried out, the erasing data for the area #1 is written at the same time and that the write-in of the erasing data must be achieved within one field period before the next packet is transmitted.
Accordingly, in this case it is carried out that the read-out for the area #0 is performed normally as well as the write-in of the erasing data for the area #1 is performed in the vertical or horizontal blanking period or that the read-out for the area #0 and the write-in of the erasing data for the area #1 are made high and achieved in a time sharing manner. However, according to the former method, since within the very short period i.e. blanking period the erasing data must be written in all of the area #1, the memories 34 and 35 must be very high speed ones. While, according to the latter method, since it takes the time sharing process, high speed memories are necessary for the memories 34 and 35, too, especially since the similar time sharing process is achieved for the other areas #2 and #3, more higher speed memories are required as the memories 34 and 35 or owing to the speed of the memories 34 and 35 the number of the areas is limited. Further, with any of the methods the peripheral circuit becomes rather complicated in construction.
If a number of small capacity chips are used as the memories 34 and 35 and one chip or more is allocated to every one of the areas #0 to #3, the read-out and write-in can be freely carried out at the chip unit so that the problem of high speed never occurs. However, this results in the increase of the number of chips and hence the cost becomes high, the apparatus becomes large in size and the power consumption is increased. Recently, such tendency appears that the capacity of a memory increases per one chip and the cost of one bit becomes low, so that it must be avoided to use a number of small capacity memories.
Accordingly, the present invention is to solve the problem when the memories 34 and 35 have the area for plural page amounts.